Basic Compiler v2.0 Free Download

Basic Compiler v2.0

Introduction

The Xilinx® LogiCORE™ IP DUC/DDC Compiler

implements high-performance, optimized Digital Upand

Down-Converter modules for use in wireless base

stations and other suitable applications. In addition to a

wide range of parameter options, resource trade-off

options are available to tailor the core to a particular

application.

Features

•  Generates Digital Up-Converter modules for a 

range of output sample rates between 30.76 and

    245.76 MHz

• Generates Digital Down-Converter modules for a 

range of input sample rates between 30.76 and

   184.32 MHz

• Supports LTE (1.4, 3, 5, 10, 15 and 20 MHz 

channels), TD-SCDMA (1.6 MHz channel) and       WCDMA 

(5 MHz channel)

• Supports up to 30 carriers (maximum dependent 

upon wireless standard and channel bandwidth)

• Implementation options to configure clock rate, 

enable optional control signals, and set resource  

usage preferences

• Supports Fs/4 IF down-mixing in DDC

configuration

• Supports programmable carrier frequencies

(within the limits imposed by wireless standard)

• Supports fixed carrier phase offsets between 0 and 

2

• Supports selectable carrier relative gain levels

• Data interfaces compliant with AXI4-Stream

standard, allowing simple integration into signal

processing data flows

• Easy-to-use programming interface compliant

with AMBA® 3 APB specification

• Graphical User Interface (GUI) features: resource

and latency estimation, frequency and phase raster

reporting

• For use with Xilinx CORE Generator™ tool v14.3

and Vivado™ Design Suite 2012.3.

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